C HAPTER 1: D ESIGN F LOW
G RAPHICAL U SER I NTERFACE D ESIGN F LOW
Table 1. Commands for Common Compiler Flows
Flow
Full compilation
flow
SignalProbe ?
flow
Early timing
estimate flow
Description
Performs a full compilation of the
current design.
Routes user-specified signals to output
pins without affecting the existing
fitting in a design, so that you can debug
signals without completing a full
compilation.
Performs a partial compilation, but stops
and generates early timing estimates
before the Fitter is complete.
Quartus II Command
from Processing Menu
Start Compilation
command
Start SignalProbe
Compilation command
Start Early Timing
Estimate command
f
For Information About
Using compilation flows
Refer To
“About Compilation Flows” in Quartus II
Help
The following steps describe the basic design flow for using the Quartus II
GUI:
1.
2.
3.
4.
5.
To create a new project and specify a target device or device family, on
the File menu, click New Project Wizard .
Use the Text Editor to create a Verilog HDL, VHDL, or Altera
Hardware Description Language (AHDL) design.
Use the Block Editor to create a block diagram with symbols that
represent other design files, or to create a schematic.
Use the MegaWizard ? Plug-In Manager to generate custom variations
of megafunctions and IP functions to instantiate in your design, or
create a system-level design by using SOPC Builder or DSP Builder.
Specify any initial design constraints using the Assignment Editor, the
Pin Planner, the Settings dialog box, the Device dialog box, the Chip
Planner, the Design Partitions window, or the Design Partition Planner.
A LTERA C ORPORATION
I NTRODUCTION TO THE Q UARTUS II S OFTWARE
5
相关PDF资料
SW-QUARTUS-SE-FLT SUBSCRIPTION FLOATALL REPL
SW006012 C COMPILER FOR DSPIC30F FAMILY
SW006013 C COMPILER MPLAB FOR DSPIC DSC
SW006015 C COMPILER MPLAB C32
SW300003-EVAL LIBRARY SOFT MODEM-EVAL ONLY
SW300010-EVAL SPEECH RECOG LIBRARY-EVAL ONLY
SW300040-EVAL LIBRARY NOISE SUPPR-EVAL ONLY
SW300060-EVAL LIBRARY ACOUSTIC ECHO-EVAL ONLY
相关代理商/技术参数
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